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E2F0023-29-83
Semiconductor MSM7654
Semiconductor NTSC/PAL Digital Video Encoder
This version: Aug. 1999 MSM7654 Previous version: Dec. 1998
GENERAL DESCRIPTION
The MSM7654, which is a digital video encoder supporting NTSC/PAL formats, converts digital image data to an analog video signal. The encoder can receive the digital image or RGB digital image signals conforming to ITU-R BT.601 as an input signal. The encoder can output simultaneously the composite video and S-video signals, and it can also output the RGB analog signal by switching. The encoder can control luminance (Y) signal output levels of the composite video and S-video signals.
FEATURES
* Video signal system: NTSC/PAL * Scanning system: interlaced/noninterlaced (NTSC : 262 lines/PAL : 312 lines) * Input digital level: conforms to ITU-R BT.601 (CCIR601) * Input-output timing: conforms to ITU-R BT.656 or ITU-R BT.624-4 * Input signal sampling ratio : Y:Cb:Cr = 4:2:2 or 4:1:1/R:G:B = 8:8:8 * Supported input interface * ITU-R BT.656 * YCbCr format (8-bit input) * ITU-R BT.601 (8-bit (Y) + 8-bit (CbCr) input) * RGB (24-bit input) * Pixel frequency (Sampling frequency) : * 12.272727 MHz (24.545454 MHz) : NTSC Square Pixel * 13.5 MHz (27 MHz) : NTSC/PAL ITU-R BT.601 * 14.318182 MHz (28.636364 MHz) : NTSC 4Fsc * 14.75 MHz (29.5 MHz) : PAL Square Pixel * Output format * Selectable composite & S-video or RGB * 37.5 W driving capability * Master or slave operation (slave operation only in ITU-R BT.656 mode) * Internal 3ch 10-bit DAC * 3-bit title/graphics can be displayed (only for composite and S-video signals) * Color bar function * I2C-bus host interface function * Brightness level adjust of 100% to 68.75% (only for composite and S-video signals) * GENLOCK control * 3.3 V single power supply (each I/O pin is 5 V tolerable) * Package 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSM7654GA)
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APPLICATIONS
* Video CD * Video game equipment * Electronic still cameras * Video filing systems * Video cameras * Videophones * Multimedia equipment * Video printers * Videoconferencing systems * Scanners * Video graphics boards * Monitoring systems
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BLOCK DIAGRAM
Semiconductor
RESET_L OLC OLR OLG OLB YUV Color Generator Y Level Converter U Level Converter V Level Converter RGB YUV Converter Color Burst Generator Subcarrier Generator Overlay Control Black & Blank Pedestal Interpolator + LPF Interpolator + LPF LPF
DAC
YA (R)
YD[7:0] Prologue Block
CD[7:0]
DAC
CVBSO (G)
BD[7:0]
DAC YUV RGB Converter VSYNC_L HSYNC_L CSYNC_L BLANK_L CLKX2
CA (B)
XVREF Sync Generator & Timing Controller I2C Control Logic Test Control Logic FS COMP
MS
GENLOCK RGBMODE
MODE[3:0]
SCL
SDA
TENB
OUTSEL
MSM7654
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PIN CONFIGURATION (TOP VIEW)

64 DGND 63 AVDD DVDD 1 2 3 SDA SCL RGBMODE MODE3 MODE2 MODE1 MODE0 MS 4 5 6 7 8 9 GENLOCK CSYNC_L VSYNC_L 10 11 12 13 14 15 HSYNC_L BLANK_L DVDD DGND 16 17 18 CD0(R0) CD1(R1)
60 CVBSO
54 XVREF
56 COMP
49 DGND 48 DVDD 47 OUTSEL 46 CLKX2 45 TENB 44 RESET_L 43 FOUT 42 BD7(B7) 41 BD6(B6) 40 BD5(B5) 39 BD4(B4) 38 BD3(B3) 37 BD2(B2) 36 BD1(B1) 35 BD0(B0) 34 DVDD 33 DGND YD7(G7) 32
61 AGND
59 AVDD
57 AGND
51 OLG 30 YD5(G5)
19
20
23
21
24
22
25
26
27
28
29
CD2(R2)
CD3(R3)
CD6(R6)
CD4(R4)
CD7(R7)
CD5(R5)
YD0(G0)
YD1(G1)
YD2(G2)
YD3(G3)
YD4(G4)
64-Pin Plastic QFP
YD6(G6)
31
50 OLR
53 OLC
52 OLB
62 YA
58 CA
55 FS
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PIN DESCRIPTIONS
Pin 1 2 3 4 5 to 8 I/O I I I I/O Symbol DVDD SDA SCL RGBMODE MODE[3:0] 3.3 V digital power supply. I2C interface data bus. I2C interface clock bus. Input signal select pin. "0" : YCbCr / "1" : RGB, Internal pull-down. Operation mode select pin. However, sleep mode is valid while RGBMODE is "0". Internal pull-down. 0000 : NTSC ITU-R BT.656 0010 : NTSC 24.52 MHz Square Pixel 0101 : NTSC 13.5 MHz YCbCr 0111 : NTSC 14.32 MHz 1000 : PAL ITU-R BT.656 1010 : PAL 29.5 MHz Square Pixel 1110 : PAL 14.75 MHz 9 I MS 1001 : PAL 27 MHz YcbCr 1101 : PAL 13.5 MHz 1111 : Sleep Mode (Valid only when RGBMODE is "0") Master/slave operation selection in other modes than ITU-R BT.656. Internal pull-down. "1" : Master / "0" : Slave Only slave mode is selected in ITU-R BT.656 mode (input of "1" is invalid) 10 11 12 13 14 15 16 17 to 24 I I I/O O I/O I/O I GENLOCK CSYNC_L VSYNC_L HSYNC_L BLANK_L DVDD DGND CD0 to CD7 GENLOCK signal I/O pin. Composite sync output pin. Vertical sync input/output pin (output mode in master mode/input mode in slave mode) Horizontal signal input/output pin (output mode in master mode/input mode in slave mode) Composite blank signal input pin. 3.3 V digital power supply. Digital GND. 8-bit digital image chrominance signal data input pins at pixel rate operation. Level conforms to ITU-R BT.601. R signal input pins in RGB input mode. CD7 is MSB. Fixed to "0" when not used. 25 to 32 I YD0 to YD7 8-bit digital image data input pins at double pixel rate operation. 8-bit digital luminance signal data input pins at pixel rate operation. Level conforms to ITU-R BT.601. G signal input pins in RGB input mode. YD7 is MSB. 33 34 35 to 42 43 44 45 46 I O I I I DGND DVDD BD0 to BD7 FOUT RESET_L TENB CLKX2 Digital GND 3.3 V digital power supply B signal input pins in RGB input mode. Fixed to "0" when not used. Field information output pin (Odd Field : "1", Even Field : "0") (Polarity can be changed by the internal register.) System reset pin. Input pin for testing. Normally fixed to "0". Internal pull-down. The user cannot use this pin. Clock input pin. 0001 : NTSC 27 MHz YCbCr 0011 : NTSC 28.64 MHz 4Fsc 0110 : NTSC 12.27 MHz Description
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PIN DESCRIPTIONS (continued)
Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 O O O I I I I I I/O I I I/O I Symbol OUTSEL DVDD DGND OLR OLG OLB OLC XVREF FS COMP AGND CA AVDD CVBSO AGND YA AVDD DGND Internal pull-down. 3.3 V digital power supply Digital GND Overlay text color (Red component). Overlay text color (Green component). Overlay text color (Blue component). Transparent control signal. "1" indicates overlay signal. External reference voltage input pin for DAC or internal reference voltage output pin. (Reference voltage for DAC) DAC full scale adjustment pin. DAC phase correction pin. Analog GND. Analog color chrominance signal output pin or B (Blue) signal output pin. 3.3 V analog power supply. Analog composite signal output pin or G (Green) signal output pin. Analog GND. Analog luminance signal output pin or R (Red) signal output pin. 3.3 V analog power supply. Digital GND. Description Video output format select pin. "0" : S-Video & Composite / "1" RGB.
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Digital Input Voltage Analog Output Current Power Consumption Storage Temperature Symbol DVDD AVDD VI IO PW TSTG Condition -- -- DVDD = 3.3 V -- -- -- Rating -0.3 to +4.5 -0.3 to +4.5 -0.3 to +5.5 70 800 -55 to +150 Unit V V mA mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage (*1) Operating Temperature 1 External Reference Voltage DA Current Setting Resistance DA Output Load Resistance Symbol DVDD AVDD Ta1 Vrefex Riadj RL Condition -- -- DVDD = AVDD = 3.3 V DVDD = AVDD = 3.3 V, Ta = 25C (*2) (*3) Min. 3.0 3.0 0 -- -- -- Typ. 3.3 3.3 25 1.25 192.5 (75//75) Max. 3.6 3.6 70 -- -- -- Unit V C V W W
(*1) (*2) (*3)
Supply an equal voltage to both DVDD and AVDD. A volume control resistor of approx. 500 W is recommendable for adjusting the output current. Indicates the value when Riadj = 192.5 W (typical value).
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = 0 to 70C, DVDD = 3.3 V 0.3 V, AVDD = 3.3 V 0.3 V) Parameter "H" Input Voltage (*1) "L" Input Voltage "H" Output Voltage "L" Output Voltage Input Leak Current Input Leak Current (with pull-down resistor) Output Leak Current Power Supply Current (operating 1) Power Supply Current (operating 2) Power Supply Current (standby 1) Symbol VIH VIL VOH VOL II IIH IO IDDO1 IDDO2 IDDS1 Condition -- -- IOH = -4 mA (*2) IOL = 4 mA (*2) VI = GND to DVDD VI = GND to DVDD VI = GND to DVDD (*3) RL = 37.5 W RL = 75 W CLKX2 = 0 MHz RESET_L = "0" RL = 37.5 W CLKX2 = 0 MHz Power Supply Current (standby 2) IDDS2 RESET_L = "0" RL = 75 W Power Supply Current (Sleep mode) I2C-bus SDA Output Voltage I2C-bus SDA Output Current Internal Reference Voltage DA Output Load Resistance Integral Linearity Differential Linearity IDDSM SDAVL SDAIO Vrefin RL RL SINL SDNL MODE [3:0] = "1111" RGBMODE = "1" Low level, IOL = 3 mA During Acknowledge -- -- -- -- -- 0 3 -- 1.0 -- -- 1.25 37.5 75 2 1 2.0 0.4 -- -- mA V mA V W W LSB LSB -- 60 65 mA -- 120 130 mA Min. 2.2 -- 0.7DVDD -- -10 20 -10 -- -- Typ. -- -- -- -- -- -- -- 180 140 Max. -- 0.8 -- 0.4 +10 250 +10 200 160 Unit V V V V mA mA mA mA mA
(*1) (*2) (*3)
Up to 5.5 V can be input to the digital input pin (5 V tolerable) VSYNC_L, HSYNC_L, GENLOCK, CSYNC_L, FOUT SDA
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Semiconductor AC Characteristics
MSM7654
(Ta = 0 to 70C, DVDD = 3.3 V 0.3 V, AVDD = 3.3 V 0.3 V) Parameter Symbol Condition PAL Square Pixel CLKX2 Frequency (*1) Fclk NTSC 4Fsc NTSC Square Pixel ITU-R BT.601/656 Input Data Setup Time 1 Input Data Setup Time 2 Input Data Hold Time 1 Input Data Hold Time 2 GENLOCK Minimum Pulse Width Output Delay Time 1 Output Delay Time 2 tS1 tS2 tH1 tH2 tW1 tD1 tD2 -- -- -- -- -- -- -- Min. -- -- -- -- 2.5 0.0 10.0 11.08 93.0 6.0 7.0 Typ. 29.5 28.636364 24.545454 27.0 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- -- -- 18.0 25.0 Unit MHz MHz MHz MHz ns ns ns ns ns ns ns
(*1)
If high precision is needed for sub-carrier/synchronization signals, clocks within 100 ppm(typ.) should be provided.
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TIMING DIAGRAMS (SWITCHING CHARACTERISTICS)
1) Setup/Hold Time The input data is fetched in the encoder at the rising edge of CLKX2. TCLKX2: Input clock period
TCLKX2 = 1/Fclk CLKX2 (Input) tS1 HSYNC_L, VSYNC_L, BLANK_L, YD, CD, BD, MS, RGBMODE, MODE, OLR, OLG, OLB, OLC, OUTSEL (Input) GENLOCK (Input) tH2
tH1 tS2 tW1
Input Timing
2) Output Delay Time
TCLKX2 = 1/Fclk CLKX2 (Input)
HSYNC_L, VSYNC_L, CSYNC_L, GENLOCK (Output) tD1 FOUT (Output) tD2 valid data
Output Timing
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3) I2C-bus Interface Input/Output Timing When writing to internal registers, written contents are set to the internal registers MR1 [7] and CR0 [2:1] during the vertical blanking period. On the other hand, written contents are immediately set to the other internal registers. (Note) Data cannot be changed when SCL is "H". Data line can be changed only when SCL is "L". The I2C-bus Interface Basic Input/Output Timing is shown below. I2C-bus AC Characteristics
(Ta = 0 to 70C, DVDD = 3.3 V 0.3 V, AVDD = 3.3 V 0.3 V) Parameter I2C-bus I2C-bus Clock Cycle Time Low Level Cycle I2C-bus High Level Cycle SDA-SCL Overlap Time Symbol tC_SCL tH_SCL tL_SCL tOV Condition Rpull_up = 4.7 kW Rpull_up = 4.7 kW Rpull_up = 4.7 kW Rpull_up = 4.7 kW Min. 200 100 100 40 Typ. -- -- -- -- Max. -- -- -- -- Unit ns ns ns ns
tOV SDA SCL S Start Condition Data Line Stable: Data Valid Change of Data Allowed MSB 1 2 7 8 9 ACK tC_SCL 1 tL_SCL 2 3-8 tH_SCL 9 ACK P Stop Condition
I2C-bus Input/Output Basic Timing
4) Reset Input Timing The reset timing is asynchronous with the clock timing. Reset AC Characteristics
(Ta = 0 to 70C, DVDD = 3.3 V 0.3 V, AVDD = 3.3 V 0.3 V) Parameter Minimum Reset Pulse Width Symbol tW2 Condition -- Min. 81.5 Typ. -- Max. -- Unit ns
CLKX2 (Input)
RESET-L (Input) tW2
Reset Timing 11/52
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MSM7654
BLOCK FUNCTIONAL DESCRIPTION
* Prologue Block This block separates input data at the ITU-R BT.656 format into a luminance signal (Y) and a chrominance signal (Cb & Cr), and also generates information concerning sync signals HSYNC_L, VSYNC_L, and BLANK_L. This block separates input data at the 27 MHz YCbCr (8-bit input) format into a luminance signal (Y) and a chrominance signal (Cb & Cr). This block separates input data at the 13.5 MHz YCbCr (16-bit input) format into a chrominance signal Cb and a chrominance signal Cr. Of the processed input data, luminance and chrominance signals other than valid pixel data are replaced by 8'h10 and 8'h80 respectively. RGB signals are converted into luminance (Y) and chrominance (Cb & Cr) signals. * Y Limiter Block This block limits the luminance input signal by clipping the lower limit of an input signal outside the ITU-R BT.601 Standard * Signals are limited to YD = 16 when YD < 16. * Signals are limited to YD = 254 when YD (input during a valid pixel period) = 255. In other cases, signals are fed as is to next processing. * C Limiter Block This block limits the chrominance signal by clipping the upper and lower limits of the input signal outside the ITU-R BT.601 Standard. CD = 1 when CD = 0 is input during a valid pixel period. CD = 254 when CD = 255 is input during a valid pixel period. * Y Level Converter Block Converts ITU-R BT.601 standard luminance signal level to DAC digital input level. * U Level Converter Block Converts ITU-R BT.601 standard chrominance signal level to DAC digital input level. * V Level Converter Block Converts ITU-R BT.601 standard chrominance signal level to DAC digital input level. * RGB YUV Level Converter Block Converts RGB signals to YUV signals at a DAC digital input level. * YUV Color Generator Block This block generates luminance and chrominance signals from overlay color signals OLR, OLG and OLB. The control signal (register CR0[3:1]) controls the output content and output level. The output content of overlay or color bar is selected with register CR0[3] and the output level of 100%, 75%, 50%, or 25% is selected with register CR0[2:1].
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* Overlay Control Block This block selects input image data or YUV Color Generator output signals. It is determined by the level of the control signal (OLC, CR [3]), as shown below: (x : don't care) CR [3] = 1, OLC = x: Selects color bar signal (YUV Color Generator output signal). CR [3] = 0, OLC = 1: Selects overlay signal (YUV Color Generator output signal). CR [3] = 0, OLC = 0: Selects input image data. * YUV to RGB Converter Block This block converts YUV signals separated by the prologue block into RGB signals. * Black & Blank Pedestal Block This block adds sync signals at the luminance side to luminance signals. * Interpolator + LPF Block This block executes data interpolation and the elimination of high frequency components by LPF for input chrominance signals. * I2C Control Logic Block This is the serial interface block based on I2C standard of Phillips Corporation. Internal registers (MR0 and MR1) and command registers (CR0 and CR1) can be set from the master side. When writing to the internal registers other than MR1 [7] (black level control) and CR0 [2:1] (overlay level), written contents are immediately set to them. It is during the vertical blanking period that written contents are set to MR1 [7] and CR0 [2:1]. * Sync Generator & Timing Controller Block This block generates sync signals and control signals. This block operates in slave mode, which performs external synchronization, and in master mode, which internally generates sync signals. * Color Burst Generator Block Outputs U and V components of amplitude of burst signals. * Subcarrier Generator Block Executes color subcarrier generation. * Low Pass Filter (LPF) Block This block performs upsampling at CLKX2 for luminance signals and chrominance signals modulated with CLKX1 divided from CLKX2. Interpolation processing is executed in this process. * DAC Block This block converts digital video signals to analog video signals with a 10-bit accuracy and outputs them. Since the analog output pins (YA, CVBSO, CA) are current outputs, these pins should be connected to external resistors. See "Analog output reference circuit in APPLICATION CIRCUIT EXAMPLE" for resistance values.
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INPUT DATA FORMAT
1) Input Level 1 (YCbCr format) The signal level specified by the ITU-R BT.601 is input. When other signal levels than specified by the ITU-R BT.601 are input, the luminance signal level is clipped to 16 to 254 and the chrominance signal level to 1 to 254. For chrominance signal input, the offset binary or 2's complement format is available by setting of internal register MR0[6].
Digital Level 100% White level 235 240(112) Digital Level
128(0)
Black Level 16 Y data 16(-112) C data
Input luminance signal level
Input chrominance signal level
2) Input Level 2 (RGB format) Two types of input level are available by setting of internal register MR1[5].
Digital Level Digital Level 100% White level 235 255
Black Level 16 Format 1 0 Format 2
Input RGB signal level 1
Input RGB signal level 2 14/52
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3) Basic Pixel Sampling Ratio 4:2:2 or 4:1:1 is supported. The internal register CR0[0] is used to control.
CLKX2 YD CD Y1 Cb1 Y2 Cr1 Y3 Cb3 Y4 Cr3 Y5 Cb5 Y6 Cr5
4:2:2 sampling at 8bit Y/8bit CbCr input
CLKX2 YD CD Y1 Cb1 Y2 Cr1 Y3 Y4 Y5 Cb5 Y6 Cr5
4:1:1 sampling at 8bit Y/8bit CbCr input
CLKX2 YD CD BD G1 R1 B1 G2 R2 B2 G3 R3 B3 G4 R4 B4 G5 R5 B5 G6 R6 B6
At RGB input
CLKX2 YD Cb1 Y1 Cr1 Y2 Cb3 Y3 Cr3 Y4 Cb5 Y5 Cr5 Y6
4:2:2 sampling at 8bit YCbCr input
CLKX2 YD Cb1 Y1 Cr1 Y2 Y3 Y4 Cb5 Y5 Cr5 Y6 Invalid data
4:1:1 sampling at 8bit YCbCr input 15/52
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4) Scanning System NTSC and PAL systems support both interlaced scanning and non-interlaced scanning. NTSC Interlaced 262.5 lines at 60 Hz NTSC Non-interlaced 262 lines at 60 Hz PAL Interlaced 312.5 lines at 50 Hz PAL Non-interlaced 312 lines at 50 Hz In the master mode, it is possible to select the desired setting from the above settings by switching the internal registers. In the master mode, only odd fields can be consecutively scanned. In the slave mode, it is possible to consecutively output odd fields or even fields by using phase information from VSYNC_L and HSYNC_L. Since either odd fields or even fields are consecutively output, the resolution is halved. However, setting of non-interlaced scanning eliminates flicker of the screen display which appears when moving of pictures is stopped in the interlaced scanning.
5) I2C Bus Format The input format of I2C-bus interface is shown below.
S Slave Address A Subaddress A Data 0 A ..... Data n A P
Symbol S Slave Address A Subaddress Data n P Start condition Slave address 1000100X. The 8th bit is write (0) signal.
Description
Acknowledge. Generated by slave Subaddress byte Write to the address specified by the subaddress. Stop condition
As described above, it is possible to write data from subaddress to subaddress continuously. Writing to discontinuous addresses is performed by repeating the Acknowledge and Stop condition formats after Data 0. If one of the following matters occurs, the encoder will not return "A" (Acknowledge). * The slave address does not match. * A non-existent subaddress is specified. * The write attribute of a register does not match "X" which is the 8th bit (LSB) of the slave address ("X" = 0 because this LSI is write only).
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INPUT TIMING 1 (ITU-R BT.656 input)
The input data is fetched in the encoder at the rising edge of a clock pulse.
CLKX2 DATA OLR, OLG, OLB, OLC
SAV(1st) SAV(2nd) SAV(3rd) SAV(4th) don't care Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1 Y11 EAV(1st) EAV(2nd) EAV(3rd) EAV(4th) don't care
VALID DATA
Input timing
Relationship Between Blank Signal and Input Image Data The blank signal is generated by the ITU-R BT.656 standard input data. The input image data is valid when the blank signal is "H".
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Semiconductor Valid Data Range
MSM7654
According to the ITU-R BT.656 standard, the pixel data immediately from SAV (4th word) to a fixed value before EVA is valid. The following figure shows the relationship between the input data at the ITU-R BT.656 format and the sync, luminance, chrominance signals which are processed inside the encoder.
Note) The values in parenthesis indicate values in PAL mode. 1716TCLKX2 (NTSC)/1728TCLKX2 (PAL) 144TCLKX2 (NTSC/PAL) SAV EAV ITU-R BT.656 standard input data 4TCLKX2 Sync signal VSYNC_L (0H) generated by input signal Sync signal VSYNC_L (1/2H) generated by input signal Sync signal HSYNC_L generated by input data 127TCLKX1 (142TCLKX1) 136TCLKX1 (146TCLKX1) 711TCLKX1 (702TCLKX1) 20TCLKX1 (20TCLKX1) 1/2H 63TCLKX1 (63TCLKX1) 4TCLKX1 (4TCLKX1) Cb0, Y00, Cr0, Y01, Cb1, Y10, Cr1, Y11.... EAV
11TCLKX1 (4TCLKX1)
4TCLKX2
9TCLKX1 (16TCLKX1) Sync signal BLANK_L generated by input data
Luminance signal separated from input data Chrominance signal separated from input data
8'h10 8'h80
Y00 Y01 Y10 Y11 Cb0 Cr0 Cb1 Cr1 1H
8'h10 8'h80
Composite signal
Relationship between input data and sync signal, luminance signal, chrominance signals
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INPUT TIMING 2 (8bit Y/8bit CbCr input, 8bit YCbCr & RGB input)
Input Data Timing Input data and sync signals are fed into the encoder at the rising edge of CLKX2. Input data is handled as valid pixel data when tSTART passes after the falling edge of HSYNC_L. Chrominance signal of input data at this time is regarded as Cb.
tSTA tSTART CLKX2 HSYNC_L YD, CD, BD, OLR, OLB, OLG,OLC BLANK_L tS1 don't care VALID DATA tH1 don't care ACTIVE VIDEO LINE tACT
Video data input timing Input data is recognized as valid pixel data when input signal BLANK_L is "H" in the tACT period. When BLANK_L is "H" during the blanking period, however, input data is not output as valid pixel data since processing to maintain blanking period is internally in-progress. The values of tSTA differ slightly between in master mode and in slave mode. The values of tSTA are as follows. In YCbCr format input mode, the values of tSTA are the same, in 8 bit (Y) + 8 bit (CbCr) mode, in 8 bit (YCbCr) mode, or in RGB mode.
In master mode Operation mode ITU-R BT.601 NTSC ITU-R BT.601 PAL 4 Fsc NTSC Square pixel NTSC Square pixel PAL tSTA - tS1 = tSTART tSTA(TCLKX2) 250 280 266 228 306 In slave mode Operation mode ITU-R BT.601 NTSC ITU-R BT.601 PAL 4 Fsc NTSC Square pixel NTSC Square pixel PAL tSTA(TCLKX2) 260 290 276 238 316
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Semiconductor Input Timing at Double Speed Pixel Rate YCbCr Format 1) Timing of Input Data to HSYNC_L
MSM7654
CLKX2 CLKX1O HSYNC_L OLR,OLG, OLB, OLC YD
Invalid Data Invalid Data tSTA Invalid Data Invalid Data Cb0 Y00 Cr0 tACT Y01 Valid Data Cb1 Y10
2) Input Timing when BLANK_L is Input
CLKX2 BLANK_L YD
Cb0 Y00 Cr0 Y01 Cb1
Input Timing at Pixel Rate and RGB YCbCr Format 1) Timing of Input Data to HSYNC_L
CLKX2 CLKX1O HSYNC_L OLR,OLG, OLB, OLC YD CD
Invalid Data Invalid Data Invalid Data tSTART Invalid Data Invalid Data Invalid Data Y0 Cb0 tACT Y1 Cr0 Valid Data Y2 Cb1
2) Input Timing when BLANK_L is Input
CLKX2 BLANK_L YD CD, BD
Y0 Cb0 Y1 Cr0 Y2 Cb1
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SYNC SIGNALS (VSYNC_L, HSYNC_L) I/O TIMING
By setting the external terminal MS or internal register, this function enables either operation in the master mode in which the sync signals HSYNC_L and VSYNC_L are internally generated or operation in the slave mode in which the encoder operates by using the external HSYNC_L and VSYNC_L (See "SETTINGS OF EACH MODE" for switching between master mode and slave mode). The field is judged by using the generated HSYNC_L and VSYNC_L.
Master Mode Output timing of HSYNC_L and VSYNC_L in master mode is as follows.
CLKX2 tD1 HSYNC_L VSYNC_L CSYNC_L tD1
Output timing 1 of internal synchronization, HSYNC_L, VSYNC_L, and CSYNC_L
VSYNC_L
HSYNC_L
CSYNC_L
YA
523 524 525 1 2 3 4 5 6 7 17 18
G (with SYNC)
523 524 525 1 2 3 4 5 6 7 17 18
Output timing 2 of internal synchronization HSYNC_L, VSYNC_L, and CSYNC_L
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Semiconductor Slave Mode Input timing of VSYNC_L and HSYNC_L in slave mode is as follows.
MSM7654
1) Odd field judgment (1) If the encoder detects the VSYNC_L falling edge between -1/4H and 0H (not including 0H), it judges information with HSYNC_L and VSYNC_L as an odd field and normally operates. (2) If the encoder detects the VSYNC_L falling edge between 0H and 1/4H (including 0H), it judges information with HSYNC_L and VSYNC_L as an odd field and normally operates.
VSYNC_L
HSYNC_L -1/4H 0H 1/4H
2) Even field judgment (1) If the encoder detects the VSYNC_L falling edge between 1/4H and 1/2H (not including 1/ 2H), it judges information with HSYNC_L and VSYNC_L as an even field and normally operates. (2) If the encoder detects the VSYNC_L falling edge between 1/2H and 3/4H (including 1/2H), it judges information with HSYNC_L and VSYNC_L as an even field and normally operates.
VSYNC_L
HSYNC_L 1/4H 1/2H 3/4H
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Semiconductor The normal vertical blanking periods cannot be obtained in the following cases:
MSM7654
(1) If the HSYNC_L peiod is longer than the standard, the vertical blanking period is output in the HSYNC_L period unless the pixel counter overflows in one line. However, in the waveform the front porch period becomes longer.
HSYNC_L (normal)
VSYNC_L
HSYNC_L (Long)
Composite (Output) Front Porch The front porch period is longer than when the normal HSYNC_L signal is input.
When the pixel counter overflows, the encoder recognizes that the HSYNC_L signal has been input when the pixel counter becomes zero and the next line starts. The following HSYNC_L signal resets the pixel counter again. Therefore, inputting such a signal not only disturbs signals in the vertical blanking period but also causes abnormal operations in the horizontal period. (2) If the HSYNC_L period is shorter than the standard, serrations may be lost. (3) If the VSYNC_L period is longer than the standard, the vertical blanking period is output as shown below. * If the number of lines is greater than the standard value, the first equalizing pulse period is longer. * If the number of lines is equal to the standard value, the contents of output signals per line are normal. * If the number of lines is smaller than the standard value, the first equalizing pulse period is shorter. (4) If the VSYNC_L period is shorter than the standard, the vertical blanking period is output as shown below. * If the number of lines is greater than the standard value, the first equalizing pulse period is longer. * If the number of lines is equal to the standard value, the contents of output signals per line are normal. * If the number of lines is smaller than the standard value, the first equalizing pulse period is shorter. 23/52
Semiconductor
MSM7654
OUTPUT FORMAT
The timing conforms to the ITU-R BT.624-4 standard. In the NTSC operation mode, the existence/non-existence of setup level is selected by setting of internal regsiters. Data level on the DAC input terminal: When the contents of 100% luminance order color bar are input into the encoder, the input level is as follows. NTSC Composite Signal (Setup 7.5IRE)
Composite Waveform (NTSC) Yellow White 945 130.8 Cyan Green Magenta Red Blue Black
DAC data Lumi (IRE)
775 718 623 565 476 418 335 324 266 224 114 4
100 89.5 72.3 61.8 45.7 35.2 20.0 18.0 7.5 0.0 -20.0 -40.0
NTSC Composite Signal (Setup 7.5)
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Semiconductor NTSC S-Video Signal (Setup 7.5IRE) * Luminance (Y) signal output
DAC data Lumi (IRE) 775 718 623 565 476 418 324 266 224 100.0 89.5 72.3 61.8 45.7 35.2 18.0 7.5 0 Y Waveform (NTSC) White Yellow Cyan Green Magenta Red Blue
MSM7654
Black
4
-40
NTSC Y Signal Output (Setup 7.5)
* NTSC chrominance (C) signal output
DAC data Lumi (IRE) 858 836 754 622 512 402 270 188 166 63 59 44 20 0 -20 -44 -59 -63 C Waveform (NTSC) Yellow Cyan Green Magenta Red Blue
Color Burst
NTSC C Signal Output (Setup 7.5)
25/52
Semiconductor NTSC S-Video Signal (Setup 0IRE) * Luminance (Y) signal output
DAC data Lumi (IRE) 959 775 713 611 548 452 389 335 287 224 114 4 133.3 100 88.6 70.1 58.7 41.3 29.9 20.0 11.4 0 -20.0 -40.0 Composite Waveform (NTSC) Yellow White Cyan Green Magenta Red Blue
MSM7654
Black
NTSC Composite Signal (Setup 0)
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Semiconductor NTSC S-Video Signal (Setup 0IRE) * Luminance (Y) signal output
DAC data Lumi (IRE) 775 713 611 548 452 389 287 224 100.0 88.6 70.1 58.7 41.3 29.9 11.4 0.0 Y Waveform (NTSC) White Yellow Cyan Green Magenta Red Blue
MSM7654
Black
4
-40.0
NTSC Y Signal Output (Setup 0)
* NTSC chrominance (C) signal output
DAC data Lumi (IRE) 860 837 758 622 512 402 266 187 164 63.2 59.0 44.7 20 0 -20 -44.7 -59.0 -63.2 C Waveform (NTSC) Yellow Cyan Green Magenta Red Blue
Color Burst
NTSC C Signal Output (Setup 0)
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Semiconductor
MSM7654
PAL Composite Signal
DAC data Lumi (IRE) 972 792 728 627 564 468 405 359 304 241 123 4 133.3 100.0 88.5 70.1 58.7 41.2 29.9 21.5 11.4 0.0 -21.5 -43.0 Composite Waveform (PAL) Yellow White Cyan Green Magenta Red Blue Black
PAL Composite Signal
28/52
Semiconductor PAL S-Video Signal * PAL luminance (Y) signal output
DAC data Lumi (IRE) 792 728 627 564 468 405 304 241 100.0 88.5 70.1 58.7 41.2 29.9 11.4 0.0 Y Waveform (PAL) White Yellow Cyan Green Magenta Red Blue
MSM7654
Black
4
-43.0
PAL Y Signal Output
* PAL chrominance (C) signal output
DAC data Lumi (IRE) 860 837 759 630 512 394 265 187 164 63.2 59.1 44.8 21.5 0 -21.5 -44.8 -59.1 -63.2 C Waveform (PAL) Yellow Cyan Green Magenta Red Blue
Color Burst
PAL C Signal Output
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Semiconductor RGB Output Waveform
MSM7654
1) Output level setting: 0-510 (MR1[5] = 0) Whether or not the Sync signal is added to the G signal is determined by setting of register CR0[6]. (CR0[6] = "0": No Sync is added, CR0[6] = "1": Sync is added)
magenta
R Signal
yellow green white cyan
510
0 G Signal (no Sync)
yellow green white cyan
magenta
510
0 G Signal (Sync)
yellow green white cyan
magenta
717
207 0
magenta
B Signal
yellow green white cyan
510
0
RGB Signal (Output Level Setting: 0-510) 30/52
black
blue
red
black
blue
red
black
blue
red
black
blue
red
Semiconductor 2) Output level setting: 32-470 (MR1[5] = 1)
MSM7654
magenta
R Signal
yellow
green
white
470
32 G Signal (no Sync)
magenta
yellow
green
white
470
32 G Signal (Sync)
magenta
yellow
green
white
677
239 0
magenta
B Signal
yellow
green
white
470
32
RGB Signal (Output Level Setting: 32-470)
black
cyan
blue
red
black
cyan
blue
red
black
cyan
blue
red
black
cyan
blue
red
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Semiconductor
MSM7654
NTSC/PAL OUTPUT TIMING
The output timing conforms to the ITU-R BT.624-4 standard. Shown below are the output waveforms of composite signals with the interlaced or noninterlaced scanning method in the NTSC or PAL operation mode. NTSC (Interlaced)
Field 1
Reference subcarrier phase
NEGATIVE HALF CYCLE Burst relative -180 to B-Y axis
POSITIVE HALF CYCLE Burst relative 180 to B-Y axis
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E Field 2 Reference subcarrier phase
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E Field 3 Reference subcarrier phase
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E Field 4 Reference subcarrier phase
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E
Output timing (Interlaced NTSC)
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Semiconductor
MSM7654
Symbol A B C D E
Name First equalizing pulse period (3H) Vertical synchronization period (3H) Second equalizing pulse period (3H) Burst pause period Vertical blanking period (20H)
Period Odd field (Even field) 259.5 to 262.5H 1 to 3H 4 to 6H 1 to 6,259.5 to 262.5H 1 to 17,259.5 to 262.5H
Output timing (Interlaced NTSC)
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Semiconductor
MSM7654
NTSC (Non-interlaced)
NEGATIVE HALF CYCLE Burst relative -180 to B-Y axis Reference subcarrier phase POSITIVE HALF CYCLE Burst relative 180 to B-Y axis
Continuous Odd Fields
260
261 A
262
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Reference subcarrier phase
260
261 A
262
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Continuous Even Fields
Reference subcarrier phase
260
261 A
262
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Reference subcarrier phase
260
261 A
262
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Output timing (Non-interlaced NTSC)
Period Continuous odd * even fields 261 to 262H 1 to 3H 4 to 6H 261 to 6H 261 to 17H
Symbol A B C D E
Name First equalizing pulse period (2H) Vertical synchronization period (3H) Second equalizing pulse period (2H) Burst pause period Vertical blanking period (19H)
Output timing (Non-interlaced NTSC) 34/52
Semiconductor PAL (Interlaced)
Burst phase +135 +V Burst phase -135 -V
MSM7654
Field 1,5
309
310
311
312 313 A
1 B
2 D
3
4 C E
5
6
7
8
23
24
25
Field 2,6
309
310
311
312 313 A
1 B D
2
3
4 C E
5
6
7
8
23
24
25
Field 3,7
309
310
311
312 313 A
1 B D
2
3
4 C E
5
6
7
8
23
24
25
Field 4,8
309
310
311
312 313 A
1 B
2 D
3
4 C E
5
6
7
8
23
24
25
Output timing (Interlaced PAL)
Symbol A B C D E Name Field 1,5 First equalizing pulse period (2.5H) Vertical synchronization period (2.5H) Second equalizing pulse period (2.5H) Burst pause period Vertical blanking period (25H) 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 6,310 to 312.5H 1 to 22.5,311 to 312.5H Field 2,6 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 5.5,308.5 to 312.5H 1 to 22.5,311 to 312.5H Period Field 3,7 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 5,311 to 312.5H 1 to 22.5,311 to 312.5H Field 4,8 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 6.5,309.5 to 312.5H 1 to 22.5,311 to 312.5H
Output timing (Interlaced PAL) 35/52
Semiconductor PAL (Non-interlaced)
Burst phase +135 +V Burst phase -135 -V
MSM7654
Continuous Odd Fields
309
310
311 A
312
1 B
2 D
3
4 C E
5
6
7
8
23
24
25
309
310
311 A
312
1 B
2 D
3
4 C E
5
6
7
8
23
24
25
Continuous Even Fields
309
310
311 A
312
1 B
2 D
3
4 C E
5
6
7
8
23
24
25
309
310
311 A
312
1 B
2 D
3
4 C E
5
6
7
8
23
24
25
Output timing (Non-interlaced PAL)
Period Continuous odd * even fields 311 to 312H 1 to 2.5H 2.5 to 5H 311 to 6H 311 to 22H
Symbol A B C D E
Name First equalizing pulse period (2H) Vertical synchronization period (2.5H) Second equalizing pulse period (2.5H) Burst pause period Vertical blanking period (24H)
Output timing (Non-interlaced PAL) 36/52
Semiconductor Equalizing Pulse, Vertical Synchronization Period
MSM7654
q w e r q 1/2H qEqualizing pulse width wVertical sync pulse width eSerration w 1/2H qBlanking level w(synchronizing + blanking level) (2/3) e(synchronizing + blanking level) (1/3) rSynchronzing level e
Setting content of equalizing pulse vertical synchronization period (TCLKX1 is sampling clock cycle in each mode) q ITU-R BT.601 NTSC ITU-R BT.601 PAL 4Fsc NTSC Square pixel NTSC Square pixel PAL 31TCLKX1 32TCLKX1 33TCLKX1 28TCLKX1 35TCLKX1 w 365TCLKX1 369TCLKX1 387TCLKX1 332TCLKX1 403TCLKX1 e 64TCLKX1 63TCLKX1 68TCLKX1 58TCLKX1 69TCLKX1 1/2H 429TCLKX1 432TCLKX1 455TCLKX1 390TCLKX1 472TCLKX1
37/52
Semiconductor Horizontal Blanking Period
1H
MSM7654
r e w q
t
q e r
w
t qHorizontal sync pulse width wBurst signal output period eBurst signal start rHorizontal blanking period (excluding front porch) tFront porch start qSynchronzing level w(synchronizing + blanking level) (1/3) e(synchronizing + blanking level) (2/3) rBlanking level tPeak to peak value of burst
Horizontal blanking period
Setting content of horizontal blanking period (TCLKX1 is sampling clock cycle in each mode) q ITU-R BT.601 NTSC ITU-R BT.601 PAL 4Fsc NTSC Square pixel NTSC Square pixel PAL 63TCLKX1 63TCLKX1 67TCLKX1 58TCLKX1 69TCLKX1 w 31TCLKX1 31TCLKX1 36TCLKX1 31TCLKX1 34TCLKX1 e 71TCLKX1 75TCLKX1 75TCLKX1 65TCLKX1 82TCLKX1 r t Total dots/1H 858 864 910 780 944 127TCLKX1 838TCLKX1 142TCLKX1 844TCLKX1 135TCLKX1 889TCLKX1 116TCLKX1 762TCLKX1 155TCLKX1 922TCLKX1
Setting content of horizontal blanking period
38/52
Semiconductor
MSM7654
SETUP LEVEL SETTING
When the NTSC operation mode is selected, one of the two kinds of setup level can be selected by setting of internal register (MR1[7]). When the setup level 0IRE (MR1[7] = "0") is selected, the Black-to-White is 100IRE. When the setup level 7.5IRE (MR1[7] = "1") is selected, the Black-to-White is 92.5IRE. However, this setup function is valid only for the NTSC mode and invalid for the PAL mode.
COLOR BAR GENERATION FUNCTION
The 25% luminance order color bar or 50% luminance order color bar or 75% luminance order color bar or 100% luminance order color bar is output by setting internal register CR0[2:1]. The output timings for each color bar color are as follows.
White Yellow Cyan Green Red Blue Black
Magenta
q w e r t y u
Output timing of each color bar color
Operation mode ITU-R BT.601 NTSC ITU-R BT.601 PAL 4Fsc NTSC Square pixel NTSC Square pixel PAL hblank q w e r t y u 1H
127TCLKX1 216TCLKX1 305TCLKX1 394TCLKX1 483TCLKX1 572TCLKX1 661TCLKX1 750TCLKX1 858TCLKX1 142TCLKX1 230TCLKX1 318TCLKX1 406TCLKX1 494TCLKX1 582TCLKX1 670TCLKX1 757TCLKX1 864TCLKX1 135TCLKX1 230TCLKX1 325TCLKX1 419TCLKX1 513TCLKX1 607TCLKX1 701TCLKX1 795TCLKX1 910TCLKX1 116TCLKX1 197TCLKX1 278TCLKX1 359TCLKX1 440TCLKX1 521TCLKX1 602TCLKX1 682TCLKX1 780TCLKX1 155TCLKX1 251TCLKX1 347TCLKX1 443TCLKX1 539TCLKX1 635TCLKX1 731TCLKX1 827TCLKX1 944TCLKX1
(TCLKX1 : sampling clock period)
Contents of color bar output timing setting 39/52
Semiconductor
MSM7654
SETTINGS OF EACH MODE
1) Switching Between Master Mode and Slave Mode By setting the external terminals MS and MODE[3:0] or internal registers MR1[3] and MR0[3:0], the encoder can select either operation in the master mode in which sync signals are internally generated or operation in the slave mode in which the encoder operates through receiving external sync signals. The switching between master mode and slave mode by settings the external terminals and internal registers are described below. If the ITU-R BT.656 standard is selected when external terminal MODE[3:0] is "0000" or internal register MR0[3:0] is "0000", the slave mode is selected irrespective of settings of external terminals and internal registers. Switching between master mode and slave mode Control by external terminal
MR0[7] MS 0 0 (External terminal is valid) 1 (Master) (Slave) MODE[3:0] "0000" Other than "0000" "0000" Other than "0000" Slave mode (specified mode other than ITU-R BT.656) Slave mode (ITU-R BT.656) Master mode (specified mode other than ITU-R BT.656) Operation mode Slave mode (ITU-R BT.656)
Control by internal register
MR0[7] MR1[3] 0 1 (Internal terminal is valid) 1 (Master) (Slave) MR0[3:0] "0000" Other than "0000" "0000" Other than "0000" Slave mode (specified mode other than ITU-R BT.656) Slave mode (ITU-R BT.656) Master mode (specified mode other than ITU-R BT.656) Operation mode Slave mode (ITU-R BT.656)
2) Setting of Sleep Mode When the external terminal RGBMODE is "0" (YCbCr mode), the sleep mode is selected when MODE[3:0] is "1111". The sleep mode cannot be selected by setting of internal registers. The sleep mode that is selected by setting of internal registers is valid only for a D/A converter through MR0[5]. 3) Settings of Input Modes (RGB and YCbCr) RGB Mode: The RGB mode is selected when the external terminal RGBMODE is "1", MODE[3:0] is a pixel frequency ("0101/01100/0111/1110"), and internal register MR0[4] is "1". YCbCr Mode: The YCbCr mode is selected when the external terminal RGBMODE is "0", MODE[3:0] is a mode other than sleep mode, and internal register MR0[4] is "0".
40/52
Semiconductor
MSM7654
FOUT OUTPUT TIMING
(1) In Master Mode * Odd Field
CLKX2 1 CLKX2 HSYNC_L VSYNC_L FOUT
* Even Field
CLKX2 1 CLKX2 HSYNC_L VSYNC_L FOUT 1/2H
(2) In Slave Mode * Odd Field
CLKX2 Tfout HSYNC_L VSYNC_L FOUT
* Even Field
CLKX2 Tfout HSYNC_L VSYNC_L FOUT 1/2H
Tfout values in slave mode depend on pixel rates. The following table lists the Tfout values to each pixel rate.
Input interface ITU-R BT.656 YCbCr (8bit) YCbCr (16bit) RGB 5 CLKX2 9 CLKX2 9 CLKX2 or 10 CLKX2 9 CLKX2 or 10 CLKX2 Tfout
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Semiconductor
MSM7654
GENLOCK FUNCTIONS
The functions of GENLOCK pin either in the master mode or in the slave mode are described below. GENLOCK Functions in Master Mode or in Slave Mode
Operation mode
MR1[0]
MR1[1] 0 Input mode Input mode Input mode Input mode
GENLOCK Function A pulse that is input to the GENLOCK pin resets the subcarrier phase. GENLOCK OFF invalidates pulses that are input to the GENLOCK pin. The internal register resets the subcarrier phase. External timing is ignored. GENLOCK OFF does not reset the subcarrier phase. External timing is ignored. An external pin can output pulses to reset the Output mode subcarrier phase. GENLOCK ON resets the subcarrier phase and its reset timing is output. An external pin can output pulses to reset the subcarrier phase.GENLOCK OFF does not reset the subcarrier phase and its reset timing is not output. An external pin cannot output pulses. Output mode GENLOCK ON with MR1[1] resets the subcarrier phase but its reset timing is not output. An external pin cannot output pulses. Output mode GENLOCK OFF does not reset the subcarrier phase and its reset timing is not output.
0 (External GENLOCK: valid) Slave mode 1 (Internal register: valid)
(GENLOCK ON) 1 (GENLOCK OFF) 0 (GENLOCK ON) 1 (GENLOCK OFF) 0 (GENLOCK ON)
0 (External GENLOCK: valid) 1 (GENLOCK OFF) Master mode 0 1 (Internal register: valid) (GENLOCK ON) 1 (GENLOCK OFF) Output mode
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Semiconductor Slave Mode
MSM7654
When in the slave mode, the encoder can receive the subcarrier-phase reset signal from the external GENLOCK pin. The subcarrier-phase pulse should be input at the timing that meets the AC characteristics. If the GENLOCK pulse is input to the encoder in the NTSC mode, the subcarrier phase is reset when the pulse reaches the 4th field. And if the GENLOCK pulse is input to the encoder in the PAL mode, the subcarrier phase is reset when the pulse reaches the eighth field. 5 CLKX2 pulses (Genlock setup time: Tgen) are required for the time from when the reset signal is input to the GENLOCK pin to when the internal GENLOCK flag is set. Thus, if the GENLOCK pulse is input 5 CLKX2 pulses before the HSYNC_L and VSYNC_L signals at the first field are input, the subcarrier phase is reset at the first field after the first input even if the internal state of the encoder is any field. The subcarrier phase, however, cannot be reset if the GENLOCK pin is fixed high. (1) Input Timing (Slave mode)
CLKX2 Tgen GENLOCK (input) CLKX1 (Internal signal) Genlock flag (Internal signal) HSYNC_L (Input) VSYNC_L (Input)
GENLOCK Input Timing
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Semiconductor Master Mode
MSM7654
If the external GENLOCK pin is valid (MR1[0] = "0"), the subcarrier-phase reset signal is output from the GENLOCK pin. When the encoder is in the NTSC mode, the signal is output at the falling edge of a HSYNC_L or VSYNC_L signal at the 4th field. When in the PAL mode, the signal is output at the falling edge of a HSYNC_L or VSYNC_L signal at the 8th field. The pulse width of GENLOCK is equivalent to two cycles of CLKX2. (2) Output Timing (Master mode) (NTSC)
Field 1 CVBSO 260 HSYNC_L VSYNC_L GENLOCK 261 262 263 1 2 3 4 5 6
Field 2 CVBSO 260 HSYNC_L VSYNC_L GENLOCK 261 262 263 1 2 3 4 5 6
Field 3 CVBSO 260 HSYNC_L VSYNC_L GENLOCK 261 262 263 1 2 3 4 5 6
Field 4 CVBSO 260 HSYNC_L VSYNC_L GENLOCK 261 262 263 1 2 3 4 5 6
CLKX2 VSYNC_L (output) 2 CLKX2 GENLOCK 4th field (NTSC) or 8th field (PAL)
GENLOCK Output Timing 44/52
Semiconductor
MSM7654
3-BIT TITLE/GRAPHICS MULTI-FUNCTION
When composite or S-video output is selected, it is possible to impose characters or graphics on the image by inputting the overlay color RGB signal from the external pins OLR, OLG, and OLB. Switching between overlay input and image data output is made by using the external pin OLC. When the RGB signal output is selected, the graphics multi-function is invalid. If the input image signal does not exist, the blue back display can be output by setting OLC and OLB to "1". The overlay input timing in the ITU-R BT.656 input mode is different from that in the 8-bit YCbCr or RGB input mode. The overlay input data in the ITU-R BT.656 input mode becomes valid immediately after fetching the 4th EAV signal. The overlay input data in the 8-bit YCbCr or RGB input mode becomes valid after HSYNC_L becomes "L" and Tstart passes and 4 CLKX2 pulses are input. In the above two cases, the OLC input should be "H" when data becomes valid. However, "data becomes valid" means that data is internally processed, and does not means that data can be output.
CLKX2 DATA OLC OLR, OLG OLB
don't care VALID DATA VALID DATA VALID DATA VALID DATA don't care SAV(1st) SAV(2nd) SAV(3rd) SAV(4th) Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1 Y11 EAV(1st) EAV(2nd) EAV(3rd) EAV(4th)
Overlay input timing (ITU-R BT.656 input mode)
CLKX2 HSYNC_L
OLC OLR, OLG, OLB YD
Invalid Data Invalid Data Valid Data
Invalid Data
Invalid Data
Cb0
Y00
Cr0
Y01
Cb1
Y10
tSTA
4 CLKX2
Overlay input timing (8-bit YCbCr or RGB input mode)
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Semiconductor
MSM7654
INTERNAL REGISTERS
All registers can be written. Details of the internal registers are described below.
Register name MR0 (Mode register) R/W Write Only Sub-address 00 MR0 [7] Item to be set Override Description Switching between the external terminal and internal register settings(for the operation mode) *0 : External terminal setting enabled 1 : Internal register setting enabled MR0 [6] Chroma format Chrominance signal input format *0 : Offset binary 1 : 2's complement MR0 [5] DAC sleep control MR0 [4] RGBMODE DAC sleep mode Control *0 : DAC active 1 : DAC sleep Input signal switching *0 : YCbCr 1 : RGB Valid only in MODE [3:0] set as follows : (0101/0110/0111/1101/1110) MR0 [3:0] Video mode select Operation mode switching Corresponds to the external MODE [3:0] pin. Logic & DAC Sleep mode cannot be set. The sleep mode by the register is valid for only DAC through MR0[5]. *0000 : NTSC ITU-R BT.656 0001 : NTSC 27 MHz YCbCr 0010 : NTSC 24.52 MHz Square Pixel 0011 : NTSC 28.64 MHz 4Fsc 0101 : NTSC 13.5 MHz YCbCr 0110 : NTSC 12.27 MHz 0111 : NTSC 14.32 MHz 1000 : PAL ITU-R BT.656 1001 : PAL 27 MHz YcbCr 1010 : PAL 29.5 MHz Square Pixel 1101 : PAL 13.5 MHz 1110 : PAL 14.75 MHz 1111 : invalid
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Semiconductor
MSM7654
Register name MR1 (Mode register)
R/W Write Only
Sub-address 01 MR1 [7]
Item to be set Black level Control
Description Black level setup Note : Valid in NTSC mode only *0 : Black level 0IRE 1 : Black level 7.5IRE
MR1 [6]
Counter Control
Non-standard signal input mode switching *0 : Corresonds to standard signal only 1 : Corresponds to standard and non-standard signals. (The field is normally judged when a signal, in which the number of lines per field is different, is input.)
MR1 [5]
RGB input Level
RGB input level switching RGB input level *0 : 0 to 255 1 : 16 to 235 RGB output level *0 : 0 to 510 1 : 32 to 470
MR1 [4]
OUTSEL
Output signal switching *0 : S-video/composite 1 : RGB
MR1 [3]
Master/Slave
Master/Slave operation switching *0 : Slave 1 : Master
MR1 [2]
INTERLANCE
Scanning *0 : Interlace 1 : Non-interlace
MR1 [1]
Genlock Control
Genlock function On/Off control *0 : Genlock On 1 : Genlock Off External Genlock pin/internal register switching for subcarrier reset control *0 : Subcarrier phase reset signal is input or output to and from external Genlock pin. * When in master mode, the reset pulse is output one field before reset is performed. The reset pulse is output only when MR1[1] is "0". * When in slave mode, reset is performed by reset signal from external pin. 1 : Content of internal register MR1[1] is valid.
MR1 (Command Write Only Register)
01
MR1 [0]
Genlock Select
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Semiconductor
MSM7654
Register name Register)
R/W
Sub-address 02 CR0 [6]
Item to be set CSYNC output
Description Addition control of CSYNC_L at RGB *0 : No addition of CSYNC to G signal 1 : Addition of CSYNC
CR0 (Command Write Only
CR0 [5]
FOUT
FOUT polarity change *0 : Odd field "H", Even field "L" 1 : Odd field "L", Even field "H"
CR0 [4]
Trap Filter
TRAP filter On/Off control *0 : Trap filter Off 1 : Trap filter On
CR0 [3]
Color Bar
Adjusting luminance order color bar output control *0 : Input image data or overlay data 1 : Luminance order color bar
CR0 [2:1]
Overlay level
Overlay signal/adjusting luminance order color bar output level control 11 : 25% 10 : 50% 01 : 75% *00 : 100%
CR0 [0]
Sampling ratio
Sampling ratio control *0 : 4:2:2 1 : 4:1:1
CR1 (Command Write Only Register)
03
CR1 [3:0]
Luminance Level
Adjusting luminance level of input image data *0000 : 100.00% 0001 : 96.875% 0010 : 93.750% 0011 : 90.675% 0100 : 87.500% 0101 : 84.375% 0110 : 81.250% 0111 : 78.125% 1000 : 75.000% 1001 : 71.875% 1010 : 68.750%
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Semiconductor
MSM7654
FILTER CHARACTERISTICS
The characteristics of LPF used for color signal processing and interpolation filters used for upsampling processing are shown below. LPF for 422 Color Signals The following shows the characteristics when the clock frequency is 27 MHz.
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 Frequency [MHz] 5 6 7
422 Interpolation + LPF Frequency Characteristic
Interpolation Filter The following shows the characteristics when the clock frequency is 27 MHz.
0
-20
Level [dB]
-40
-60
-80
-100 0 2 4 6 8 Frequency [MHz] 10 12 14
Up Sampling Filter Frequency Characteristic
(Note) The characteristics of these filters are based on design data. 49/52
Semiconductor Trap Filter The following shows the characteristics when the clock frequency is 27 MHz.
Trap Filter (for NTSC) Frequency Characteristics 0
MSM7654
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 Frequency [MHz] 5 6 7
Trap Filter (for PAL) Frequency Characteristics 0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 Frequency [MHz] 5 6 7
(Note) The characteristics of these filters are based on design data.
50/52
Semiconductor
MSM7654
APPLICATION CIRCUIT EXAMPLE (YCbCr 16-bit input mode)
5 V or 3.3 V
RL 5 V or 3.3 V I2C Controller
RL 3.3 V 3.3 V
MS RGBMODE MODE[3:0] TENB OUTSEL OLR OLG OLB OLC
DVDD
DIP SW
AVDD
SDA
SCL
XVREF
Typ. 1.25 V 3.3 V RC CC = 0.1 F
FS
COMP LPF YA MSM7654 CVBSO R1 R1 LPF CA R1 DGND AGND CLKX2 FOUT RC = 500 VR R1 R1 LPF R1
Overlay Controller 5 V or 3.3 V YD[7:0] CD[7:0] BD[7:0] (0 fixed)
YD[7:0] CD[7:0] BD[7:0] VSYNC_L HSYNC_L BLANK_L CSYNC_L
Sample of Analog Output Circuit
YA CA CVBSO OUTPUT 150 W
3.6 mH 150 W 164 pF 164 pF
LPF (TOKO, INC-make 628LJN-1471 is recommended.)
Note: The filters shown above are samples to be referenced. Filters to be used can be selected by the user. The analog output circuit shown above is a sample when a destination connected to is terminated with 75 W load. If the connected destination is not terminated or is drived with 37.5 W load, the analog output circuit should use 75 W resistors. If the YA, CA and CVBSO pins are terminated with 37.5 W load, an operational amplifier is not used. 51/52
Semiconductor
MSM7654
PACKAGE DIMENSIONS
(Unit : mm)
Mirror finish
64-Pin Plastic QFP
52/52
E2Y0002-29-62
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan

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